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https://github.com/Proxmark/proxmark3.git
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5ea2a24839
* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame * get rid of most of the warnings when compiling the HF verilog sources * refactoring the constants in Verilog sources
39 lines
1.3 KiB
Makefile
39 lines
1.3 KiB
Makefile
include ../common/Makefile.common # for $(DETECTED_OS)
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all: fpga_lf.bit fpga_hf.bit
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clean:
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$(DELETE) *.bgn *.drc *.ncd *.ngd *_par.xrpt *-placed.* *-placed_pad.* *_usage.xml xst_hf.srp xst_lf.srp
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$(DELETE) *.map *.ngc *.xrpt *.pcf *.rbt *_auto_* *.bld *.mrp *.ngm *.unroutes *_summary.xml netlist.lst xst
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fpga_hf.ngc: fpga_hf.v fpga.ucf xst_hf.scr util.v hi_simulate.v hi_reader.v hi_iso14443a.v hi_sniffer.v hi_get_trace.v
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)xst -ifn xst_hf.scr
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fpga_lf.ngc: fpga_lf.v fpga.ucf xst_lf.scr util.v clk_divider.v lo_edge_detect.v lo_read.v lo_passthru.v lp20khz_1MSa_iir_filter.v min_max_tracker.v lf_edge_detect.v
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)xst -ifn xst_lf.scr
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%.ngd: %.ngc
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)ngdbuild -aul -p xc2s30-5-vq100 -nt timestamp -uc fpga.ucf $< $@
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%.ncd: %.ngd
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)map -p xc2s30-5-vq100 $<
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%-placed.ncd: %.ncd
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$(DELETE) $@
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$(XILINX_TOOLS_PREFIX)par $< $@
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%.bit: %-placed.ncd
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$(DELETE) $@ $*.drc $*.rbt
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$(XILINX_TOOLS_PREFIX)bitgen $< $@
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.PHONY: all clean help
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help:
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@echo Multi-OS Makefile, you are running on $(DETECTED_OS)
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@echo Possible targets:
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@echo + all - Make fpga.bit, the FPGA bitstream
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@echo + clean - Clean intermediate files, does not clean fpga.bit
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