mirror of
https://github.com/Proxmark/proxmark3.git
synced 2024-11-23 14:00:18 -08:00
b8ed9975e5
* use different data types for commands and responses * use variable length responses * maintain client/flasher compatibility with old format (e.g. when using old bootloader) * maintain bootloader compatibility with old format (e.g. when using old or RRG flasher.exe) * fix length of version string in appmain.c
319 lines
9.2 KiB
C
319 lines
9.2 KiB
C
//-----------------------------------------------------------------------------
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// Main code for the bootloader
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//-----------------------------------------------------------------------------
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#include "proxmark3.h"
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#include "usb_cdc.h"
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void DbpString(char *str) {
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uint8_t len = 0;
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while (str[len] != 0x00) {
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len++;
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}
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cmd_send_old(CMD_DEBUG_PRINT_STRING,len,0,0,(uint8_t*)str,len);
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}
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struct common_area common_area __attribute__((section(".commonarea")));
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unsigned int start_addr, end_addr, bootrom_unlocked;
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extern char _bootrom_start, _bootrom_end, _flash_start, _flash_end;
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static void ConfigClocks(void)
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{
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// we are using a 16 MHz crystal as the basis for everything
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// slow clock runs at 32Khz typical regardless of crystal
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// enable system clock and USB clock
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AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK | AT91C_PMC_UDP;
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// enable the clock to the following peripherals
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AT91C_BASE_PMC->PMC_PCER =
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(1<<AT91C_ID_PIOA) |
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(1<<AT91C_ID_ADC) |
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(1<<AT91C_ID_SPI) |
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(1<<AT91C_ID_SSC) |
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(1<<AT91C_ID_PWMC) |
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(1<<AT91C_ID_UDP);
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// worst case scenario, with MAINCK = 16Mhz xtal, startup delay is 1.4ms
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// if SLCK slow clock runs at its worst case (max) frequency of 42khz
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// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
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// enable main oscillator and set startup delay
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AT91C_BASE_PMC->PMC_MOR =
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AT91C_CKGR_MOSCEN |
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PMC_MAIN_OSC_STARTUP_DELAY(8);
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// wait for main oscillator to stabilize
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS) )
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;
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// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
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// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
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// PLL output is MAINCK * multiplier / divisor = 16Mhz * 12 / 2 = 96Mhz
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AT91C_BASE_PMC->PMC_PLLR =
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PMC_PLL_DIVISOR(2) |
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PMC_PLL_COUNT_BEFORE_LOCK(0x50) |
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PMC_PLL_FREQUENCY_RANGE(0) |
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PMC_PLL_MULTIPLIER(12) |
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PMC_PLL_USB_DIVISOR(1);
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// wait for PLL to lock
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) )
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;
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// we want a master clock (MCK) to be PLL clock / 2 = 96Mhz / 2 = 48Mhz
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// datasheet recommends that this register is programmed in two operations
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// when changing to PLL, program the prescaler first then the source
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
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// wait for main clock ready signal
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
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;
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// set the source to PLL
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
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// wait for main clock ready signal
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while ( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) )
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;
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}
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static void Fatal(void)
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{
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for(;;);
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}
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void UsbPacketReceived(UsbCommand *c) {
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int i, dont_ack=0;
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volatile uint32_t *p;
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uint32_t arg0 = (uint32_t)c->arg[0];
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switch(c->cmd) {
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case CMD_DEVICE_INFO: {
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dont_ack = 1;
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arg0 = DEVICE_INFO_FLAG_BOOTROM_PRESENT
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| DEVICE_INFO_FLAG_CURRENT_MODE_BOOTROM
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| DEVICE_INFO_FLAG_UNDERSTANDS_START_FLASH;
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if(common_area.flags.osimage_present) {
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arg0 |= DEVICE_INFO_FLAG_OSIMAGE_PRESENT;
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}
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cmd_send_old(CMD_DEVICE_INFO,arg0,1,2,0,0);
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} break;
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case CMD_SETUP_WRITE: {
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/* The temporary write buffer of the embedded flash controller is mapped to the
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* whole memory region, only the last 8 bits are decoded.
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*/
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p = (volatile uint32_t *)&_flash_start;
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for(i = 0; i < 12; i++) {
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p[i+arg0] = c->d.asDwords[i];
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}
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} break;
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case CMD_FINISH_WRITE: {
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uint32_t* flash_mem = (uint32_t*)(&_flash_start);
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for (size_t j=0; j<2; j++) {
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for(i = 0+(64*j); i < 64+(64*j); i++) {
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flash_mem[i] = c->d.asDwords[i];
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}
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uint32_t flash_address = arg0 + (0x100*j);
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/* Check that the address that we are supposed to write to is within our allowed region */
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if( ((flash_address+AT91C_IFLASH_PAGE_SIZE-1) >= end_addr) || (flash_address < start_addr) ) {
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/* Disallow write */
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dont_ack = 1;
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cmd_send_old(CMD_NACK,0,0,0,0,0);
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} else {
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uint32_t page_n = (flash_address - ((uint32_t)flash_mem)) / AT91C_IFLASH_PAGE_SIZE;
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/* Translate address to flash page and do flash, update here for the 512k part */
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AT91C_BASE_EFC0->EFC_FCR = MC_FLASH_COMMAND_KEY |
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MC_FLASH_COMMAND_PAGEN(page_n) |
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AT91C_MC_FCMD_START_PROG;
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}
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// Wait until flashing of page finishes
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uint32_t sr;
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while(!((sr = AT91C_BASE_EFC0->EFC_FSR) & AT91C_MC_FRDY));
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if(sr & (AT91C_MC_LOCKE | AT91C_MC_PROGE)) {
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dont_ack = 1;
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cmd_send_old(CMD_NACK,0,0,0,0,0);
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}
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}
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} break;
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case CMD_HARDWARE_RESET: {
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usb_disable();
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AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
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} break;
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case CMD_START_FLASH: {
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if(c->arg[2] == START_FLASH_MAGIC) bootrom_unlocked = 1;
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else bootrom_unlocked = 0;
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{
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int prot_start = (int)&_bootrom_start;
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int prot_end = (int)&_bootrom_end;
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int allow_start = (int)&_flash_start;
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int allow_end = (int)&_flash_end;
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int cmd_start = c->arg[0];
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int cmd_end = c->arg[1];
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/* Only allow command if the bootrom is unlocked, or the parameters are outside of the protected
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* bootrom area. In any case they must be within the flash area.
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*/
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if( (bootrom_unlocked || ((cmd_start >= prot_end) || (cmd_end < prot_start)))
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&& (cmd_start >= allow_start) && (cmd_end <= allow_end) ) {
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start_addr = cmd_start;
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end_addr = cmd_end;
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} else {
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start_addr = end_addr = 0;
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dont_ack = 1;
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cmd_send_old(CMD_NACK,0,0,0,0,0);
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}
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}
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} break;
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default: {
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Fatal();
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} break;
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}
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if(!dont_ack) {
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cmd_send_old(CMD_ACK,arg0,0,0,0,0);
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}
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}
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static void flash_mode(int externally_entered)
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{
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start_addr = 0;
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end_addr = 0;
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bootrom_unlocked = 0;
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UsbCommand rx;
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usb_enable();
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for (volatile size_t i=0; i<0x100000; i++) {};
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for(;;) {
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WDT_HIT();
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if (cmd_receive(&rx)) {
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UsbPacketReceived(&rx);
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}
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if(!externally_entered && !BUTTON_PRESS()) {
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/* Perform a reset to leave flash mode */
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usb_disable();
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LED_B_ON();
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AT91C_BASE_RSTC->RSTC_RCR = RST_CONTROL_KEY | AT91C_RSTC_PROCRST;
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for(;;);
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}
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if(externally_entered && BUTTON_PRESS()) {
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/* Let the user's button press override the automatic leave */
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externally_entered = 0;
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}
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}
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}
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extern uint32_t _osimage_entry;
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void BootROM(void)
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{
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//------------
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// First set up all the I/O pins; GPIOs configured directly, other ones
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// just need to be assigned to the appropriate peripheral.
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// Kill all the pullups, especially the one on USB D+; leave them for
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// the unused pins, though.
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AT91C_BASE_PIOA->PIO_PPUDR =
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GPIO_USB_PU |
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GPIO_LED_A |
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GPIO_LED_B |
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GPIO_LED_C |
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GPIO_LED_D |
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GPIO_FPGA_DIN |
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GPIO_FPGA_DOUT |
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GPIO_FPGA_CCLK |
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GPIO_FPGA_NINIT |
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GPIO_FPGA_NPROGRAM |
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GPIO_FPGA_DONE |
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GPIO_MUXSEL_HIPKD |
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GPIO_MUXSEL_HIRAW |
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GPIO_MUXSEL_LOPKD |
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GPIO_MUXSEL_LORAW |
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GPIO_RELAY |
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GPIO_NVDD_ON;
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// (and add GPIO_FPGA_ON)
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// These pins are outputs
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AT91C_BASE_PIOA->PIO_OER =
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GPIO_LED_A |
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GPIO_LED_B |
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GPIO_LED_C |
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GPIO_LED_D |
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GPIO_RELAY |
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GPIO_NVDD_ON;
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// PIO controls the following pins
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AT91C_BASE_PIOA->PIO_PER =
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GPIO_USB_PU |
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GPIO_LED_A |
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GPIO_LED_B |
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GPIO_LED_C |
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GPIO_LED_D;
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// USB_D_PLUS_PULLUP_OFF();
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usb_disable();
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LED_D_OFF();
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LED_C_ON();
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LED_B_OFF();
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LED_A_OFF();
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AT91C_BASE_EFC0->EFC_FMR =
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AT91C_MC_FWS_1FWS |
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MC_FLASH_MODE_MASTER_CLK_IN_MHZ(48);
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// Initialize all system clocks
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ConfigClocks();
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LED_A_ON();
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int common_area_present = 0;
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switch(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_RSTTYP) {
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case AT91C_RSTC_RSTTYP_WATCHDOG:
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case AT91C_RSTC_RSTTYP_SOFTWARE:
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case AT91C_RSTC_RSTTYP_USER:
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/* In these cases the common_area in RAM should be ok, retain it if it's there */
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if(common_area.magic == COMMON_AREA_MAGIC && common_area.version == 1) {
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common_area_present = 1;
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}
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break;
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default: /* Otherwise, initialize it from scratch */
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break;
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}
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if(!common_area_present){
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/* Common area not ok, initialize it */
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int i; for(i=0; i<sizeof(common_area); i++) { /* Makeshift memset, no need to drag util.c into this */
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((char*)&common_area)[i] = 0;
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}
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common_area.magic = COMMON_AREA_MAGIC;
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common_area.version = 1;
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common_area.flags.bootrom_present = 1;
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}
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common_area.flags.bootrom_present = 1;
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if(common_area.command == COMMON_AREA_COMMAND_ENTER_FLASH_MODE) {
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common_area.command = COMMON_AREA_COMMAND_NONE;
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flash_mode(1);
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} else if(BUTTON_PRESS()) {
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flash_mode(0);
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} else if(_osimage_entry == 0xffffffffU) {
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flash_mode(1);
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} else {
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// jump to Flash address of the osimage entry point (LSBit set for thumb mode)
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__asm("bx %0\n" : : "r" ( ((int)&_osimage_entry) | 0x1 ) );
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}
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}
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