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1b902aa01a
* FPGA Hi-Simulate: Formatted code * FPGA Hi-Simulate: Fixed documantation * FPGA Hi-Simulate: Freed up 4 LUTs * FPGA Hi-Simulate: Added 212kHz SSP-Clock option * Legic: Moved card simulator into separate file & cleaned interface. Reader and card simulation have almost no common code. Moreover the sim uses an SSP Clock at 212kHz for all timings to prevent any drifting from the PRNG. This clock speed is not available in reader simulation mode (SSP runs at up to 3.4MHz, and changes speed between TX and RX). For these reasons having the code in separate files makes it significantly cleaner. * Legic: Implemented RX and TX for card simulation * Legic: Implemented setup phase for card simulation * Legic: Implemented read command for card simulation * Legic: Implemented write command for card simulation
20 lines
672 B
C
20 lines
672 B
C
//-----------------------------------------------------------------------------
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// (c) 2009 Henryk Plötz <henryk@ploetzli.ch>
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// 2018 AntiCat
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// LEGIC RF emulation public interface
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//-----------------------------------------------------------------------------
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#ifndef __LEGICRFSIM_H
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#define __LEGICRFSIM_H
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#include "proxmark3.h"
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extern void LegicRfSimulate(uint8_t tagtype);
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#endif /* __LEGICRFSIM_H */
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