mirror of
https://github.com/Proxmark/proxmark3.git
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867e10a5fd
* merge cmd.c into usb_cdc.c * move back usb_cdc.[ch] to common/ * declare low level functions usb_read() and usb_write() and more functions as static * use cmd_receive() in bootrom.c and appmain.c * remove unused memory wasting csrTab[100] in usb_cdc.c * replace more byte_t by uint8_t * more whitespace fixes
119 lines
3.9 KiB
C
119 lines
3.9 KiB
C
//-----------------------------------------------------------------------------
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// piwi, 2019
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//
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// This code is licensed to you under the terms of the GNU GPL, version 2 or,
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// at your option, any later version. See the LICENSE.txt file for the text of
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// the license.
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//-----------------------------------------------------------------------------
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// Routines to get sample data from FPGA.
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//-----------------------------------------------------------------------------
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#include "hfsnoop.h"
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#include "proxmark3.h"
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#include "BigBuf.h"
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#include "util.h"
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#include "apps.h"
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#include "usb_cdc.h"
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#include "fpga.h"
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#include "fpgaloader.h"
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static void RAMFUNC optimizedSnoop(void)
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{
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int n = BigBuf_max_traceLen() / sizeof(uint16_t); // take all memory
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uint16_t *dest = (uint16_t *)BigBuf_get_addr();
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uint16_t *destend = dest + n;
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16); // Setting Frame mode, 16 bits per word
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// Reading data loop
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while(dest <= destend)
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{
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if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)
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{
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*dest = (uint16_t)(AT91C_BASE_SSC->SSC_RHR);
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dest++;
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}
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}
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//Resetting Frame mode (First set in fpgaloader.c)
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) | AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
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}
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void HfSnoop(int samplesToSkip, int triggersToSkip)
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{
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BigBuf_free(); BigBuf_Clear();
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Dbprintf("Skipping first %d sample pairs, Skipping %d triggers.\n", samplesToSkip, triggersToSkip);
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int trigger_cnt;
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LED_D_ON();
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// Select correct configs
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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// Set up the synchronous serial port
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FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SNOOP);
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// connect Demodulated Signal to ADC:
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SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SNOOP);
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SpinDelay(100);
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AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(16); // Setting Frame Mode For better performance on high speed data transfer.
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trigger_cnt = 0;
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uint16_t r = 0;
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while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
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WDT_HIT();
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
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r = (uint16_t)AT91C_BASE_SSC->SSC_RHR;
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r = MAX(r & 0xff, r >> 8);
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if (r >= 240) {
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if (++trigger_cnt > triggersToSkip)
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break;
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}
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}
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}
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if(!BUTTON_PRESS()) {
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int waitcount = samplesToSkip; // lets wait 40000 ticks of pck0
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while(waitcount != 0) {
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if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY))
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waitcount--;
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}
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optimizedSnoop();
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Dbprintf("Trigger kicked! Value: %d, Dumping Samples Hispeed now.", r);
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}
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DbpString("HF Snoop end");
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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LED_D_OFF();
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}
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void HfPlot(void)
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{
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uint8_t *buf = ToSend;
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uint8_t *this_buf = buf;
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FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
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FpgaSetupSsc(FPGA_MAJOR_MODE_HF_GET_TRACE);
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AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS; // Disable DMA Transfer
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AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) this_buf; // start transfer to this memory address
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AT91C_BASE_PDC_SSC->PDC_RCR = USB_CMD_DATA_SIZE; // transfer this many samples
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buf[0] = (uint8_t)AT91C_BASE_SSC->SSC_RHR; // clear receive register
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AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN; // Start DMA transfer
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FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_GET_TRACE); // let FPGA transfer its internal Block-RAM
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LED_B_ON();
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for(size_t i = 0; i < FPGA_TRACE_SIZE; i += USB_CMD_DATA_SIZE) {
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// prepare next DMA transfer:
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uint8_t *next_buf = buf + ((i + USB_CMD_DATA_SIZE) % (2 * USB_CMD_DATA_SIZE));
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AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t)next_buf;
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AT91C_BASE_PDC_SSC->PDC_RNCR = USB_CMD_DATA_SIZE;
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size_t len = MIN(FPGA_TRACE_SIZE - i, USB_CMD_DATA_SIZE);
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while (!(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX))) ; // wait for DMA transfer to complete
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cmd_send(CMD_DOWNLOADED_RAW_ADC_SAMPLES_125K, i, len, FPGA_TRACE_SIZE, this_buf, len);
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this_buf = next_buf;
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}
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// Trigger a finish downloading signal with an ACK frame
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cmd_send(CMD_ACK, 1, 0, FPGA_TRACE_SIZE, 0, 0);
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LED_B_OFF();
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FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
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}
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