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https://github.com/Proxmark/proxmark3.git
synced 2025-03-12 04:35:36 -07:00
Hitag fixes (#887)
* don't display error message during 'lf search' when no Hitag tag is present * remove superfluous options in 'lf hitag read' * fix setting of default threshold when selecting FPGA_CMD_SET_EDGE_DETECT_THRESHOLD major mode * some refactoring
This commit is contained in:
pwpiwi
GitHub
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e938f71011
commit
00848e096b
@ -39,7 +39,8 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_CMD_SET_CONFREG (1<<12)
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// LF
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#define FPGA_CMD_SET_DIVISOR (2<<12)
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#define FPGA_CMD_SET_USER_BYTE1 (3<<12)
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD (3<<12)
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// HF
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#define FPGA_CMD_TRACE_ENABLE (2<<12)
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@ -61,9 +62,8 @@ void SetAdcMuxFor(uint32_t whichGpio);
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#define FPGA_LF_ADC_READER_FIELD (1<<0)
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// Options for LF_EDGE_DETECT
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#define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD FPGA_CMD_SET_USER_BYTE1
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#define FPGA_LF_EDGE_DETECT_READER_FIELD (1<<0)
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#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (1<<1)
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#define FPGA_LF_EDGE_DETECT_TOGGLE_MODE (2<<0)
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// Options for the HF reader
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#define FPGA_HF_READER_MODE_RECEIVE_IQ (0<<0)
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@ -943,12 +943,12 @@ int CmdLFfind(const char *Cmd)
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PrintAndLog("\nValid EM4x05/EM4x69 Chip Found\nUse lf em 4x05readword/dump commands to read\n");
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return 1;
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}
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ans=CmdLFHitagReader("26"); // 26 = RHT2F_UID_ONLY
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if (ans==0) {
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if (getHitagUid(NULL, true)) {
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PrintAndLog("\nValid Hitag2 tag Found!");
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return 1;
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}
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ans=CmdCOTAGRead("");
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if (ans>0) {
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}
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ans = CmdCOTAGRead("");
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if (ans > 0) {
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PrintAndLog("\nValid COTAG ID Found!");
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return 1;
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}
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@ -70,7 +70,7 @@ static int CmdLFHitagList(const char *Cmd) {
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for (;;) {
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if(i > traceLen) { break; }
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if(i >= traceLen) { break; }
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bool isResponse;
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int timestamp = *((uint32_t *)(got+i));
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@ -208,7 +208,7 @@ static int CmdLFHitagSim(const char *Cmd) {
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}
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static bool getHitagUid(uint32_t *uid) {
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bool getHitagUid(uint32_t *uid, bool quiet) {
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// ToDo: this is for Hitag2 only (??)
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UsbCommand c = {CMD_READER_HITAG, {RHT2F_UID_ONLY}};
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@ -217,12 +217,12 @@ static bool getHitagUid(uint32_t *uid) {
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UsbCommand resp;
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if (!WaitForResponseTimeout(CMD_ACK, &resp, 2500)) {
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PrintAndLogEx(WARNING, "timeout while waiting for reply.");
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if (!quiet) PrintAndLogEx(WARNING, "timeout while waiting for reply.");
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return false;
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}
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if (resp.arg[0] == false) {
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PrintAndLogEx(DEBUG, "DEBUG: Error - failed getting UID");
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if (!quiet) PrintAndLogEx(DEBUG, "DEBUG: Error - failed getting UID");
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return false;
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}
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@ -246,7 +246,7 @@ static int CmdLFHitagInfo(const char *Cmd) {
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// read UID
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uint32_t uid = 0;
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if (getHitagUid(&uid) == false)
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if (getHitagUid(&uid, false) == false)
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return 1;
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PrintAndLogEx(SUCCESS, "UID: %08X", uid);
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@ -271,32 +271,19 @@ int CmdLFHitagReader(const char *Cmd) {
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hitag_function htf = param_get32ex(Cmd, 0, 0, 10);
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switch (htf) {
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case 01: { //RHTSF_CHALLENGE
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case RHTSF_CHALLENGE: {
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c = (UsbCommand){ CMD_READ_HITAG_S };
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num_to_bytes(param_get32ex(Cmd, 1, 0, 16), 4, htd->auth.NrAr);
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num_to_bytes(param_get32ex(Cmd, 2, 0, 16), 4, htd->auth.NrAr+4);
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c.arg[1] = param_get64ex(Cmd, 3, 0, 0); //firstpage
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c.arg[2] = param_get64ex(Cmd, 4, 0, 0); //tag mode
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} break;
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case 02: { //RHTSF_KEY
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case RHTSF_KEY: {
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c = (UsbCommand){ CMD_READ_HITAG_S };
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num_to_bytes(param_get64ex(Cmd, 1, 0, 16), 6, htd->crypto.key);
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c.arg[1] = param_get64ex(Cmd, 2, 0, 0); //firstpage
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c.arg[2] = param_get64ex(Cmd, 3, 0, 0); //tag mode
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} break;
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case 03: { //RHTSF_CHALLENGE BLOCK
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c = (UsbCommand){ CMD_READ_HITAG_S_BLK };
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num_to_bytes(param_get32ex(Cmd, 1, 0, 16), 4, htd->auth.NrAr);
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num_to_bytes(param_get32ex(Cmd, 2, 0, 16), 4, htd->auth.NrAr+4);
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c.arg[1] = param_get64ex(Cmd, 3, 0, 0); //firstpage
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c.arg[2] = param_get64ex(Cmd, 4, 0, 0); //tag mode
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} break;
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case 04: { //RHTSF_KEY BLOCK
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c = (UsbCommand){ CMD_READ_HITAG_S_BLK };
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num_to_bytes(param_get64ex(Cmd, 1, 0, 16), 6, htd->crypto.key);
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c.arg[1] = param_get64ex(Cmd, 2, 0, 0); //firstpage
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c.arg[2] = param_get64ex(Cmd, 3, 0, 0); //tag mode
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} break;
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case RHT2F_PASSWORD: {
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num_to_bytes(param_get32ex(Cmd, 1, 0, 16), 4, htd->pwd.password);
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} break;
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@ -322,8 +309,6 @@ int CmdLFHitagReader(const char *Cmd) {
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PrintAndLog(" HitagS (0*):");
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PrintAndLog(" 01 <nr> <ar> (Challenge) <firstPage> <tagmode> read all pages from a Hitag S tag");
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PrintAndLog(" 02 <key> (set to 0 if no authentication is needed) <firstPage> <tagmode> read all pages from a Hitag S tag");
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PrintAndLog(" 03 <nr> <ar> (Challenge) <firstPage> <tagmode> read all blocks from a Hitag S tag");
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PrintAndLog(" 04 <key> (set to 0 if no authentication is needed) <firstPage> <tagmode> read all blocks from a Hitag S tag");
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PrintAndLog(" Valid tagmodes are 0=STANDARD, 1=ADVANCED, 2=FAST_ADVANCED (default is ADVANCED)");
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PrintAndLog(" Hitag1 (1*):");
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PrintAndLog(" (not yet implemented)");
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@ -356,11 +341,11 @@ int CmdLFHitagReader(const char *Cmd) {
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return 1;
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}
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uint32_t id = bytes_to_num(resp.d.asBytes,4);
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uint32_t id = bytes_to_num(resp.d.asBytes, 4);
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if (htf == RHT2F_UID_ONLY){
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PrintAndLog("Valid Hitag2 tag found - UID: %08x",id);
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} else {
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PrintAndLog("Valid Hitag2 tag found - UID: %08x", id);
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if (htf != RHT2F_UID_ONLY) {
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PrintAndLogEx(SUCCESS, "Dumping tag memory...");
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char filename[256];
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FILE* pf = NULL;
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@ -11,7 +11,11 @@
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#ifndef CMDLFHITAG_H__
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#define CMDLFHITAG_H__
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#include <stdint.h>
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#include <stdbool.h>
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extern int CmdLFHitag(const char *Cmd);
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extern int CmdLFHitagReader(const char *Cmd);
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extern bool getHitagUid(uint32_t *uid, bool quiet);
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#endif
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BIN
fpga/fpga_lf.bit
BIN
fpga/fpga_lf.bit
Binary file not shown.
@ -3,6 +3,26 @@
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// iZsh <izsh at fail0verflow.com>, June 2014
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//-----------------------------------------------------------------------------
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// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
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// Note: the definitions here are without shifts
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// Commands:
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`define FPGA_CMD_SET_CONFREG 1
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`define FPGA_CMD_SET_DIVISOR 2
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`define FPGA_CMD_SET_EDGE_DETECT_THRESHOLD 3
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// Major modes:
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`define FPGA_MAJOR_MODE_LF_ADC 0
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`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
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`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
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// Options for LF_ADC
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`define FPGA_LF_ADC_READER_FIELD 1
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// Options for LF_EDGE_DETECT
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`define FPGA_LF_EDGE_DETECT_READER_FIELD 1
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`define FPGA_LF_EDGE_DETECT_TOGGLE_MODE 2
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`include "lo_read.v"
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`include "lo_passthru.v"
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`include "lo_edge_detect.v"
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@ -30,21 +50,23 @@ module fpga_lf(
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reg [15:0] shift_reg;
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reg [7:0] divisor;
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reg [8:0] conf_word;
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reg [7:0] user_byte1;
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reg [7:0] lf_ed_threshold;
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always @(posedge ncs)
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begin
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case (shift_reg[15:12])
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4'b0001: // FPGA_CMD_SET_CONFREG
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`FPGA_CMD_SET_CONFREG:
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begin
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conf_word <= shift_reg[8:0];
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if (shift_reg[8:0] == 9'b000000001)
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begin // LF edge detect
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user_byte1 <= 127; // default threshold
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if (shift_reg[8:6] == `FPGA_MAJOR_MODE_LF_EDGE_DETECT)
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begin
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lf_ed_threshold <= 127; // default threshold
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end
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end
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4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
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4'b0011: user_byte1 <= shift_reg[7:0]; // FPGA_CMD_SET_USER_BYTE1
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`FPGA_CMD_SET_DIVISOR:
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divisor <= shift_reg[7:0];
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`FPGA_CMD_SET_EDGE_DETECT_THRESHOLD:
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lf_ed_threshold <= shift_reg[7:0];
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endcase
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end
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@ -62,7 +84,6 @@ wire [2:0] major_mode = conf_word[8:6];
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// For the low-frequency configuration:
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wire lf_field = conf_word[0];
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wire lf_ed_toggle_mode = conf_word[1]; // for lo_edge_detect
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wire [7:0] lf_ed_threshold = user_byte1;
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//-----------------------------------------------------------------------------
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// And then we instantiate the modules corresponding to each of the FPGA's
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@ -106,17 +127,17 @@ lo_edge_detect le(
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// 001 -- LF edge detect (generic)
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// 010 -- LF passthrough
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_clk (major_mode, ssp_clk, lr_ssp_clk, le_ssp_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_din (major_mode, ssp_din, lr_ssp_din, 1'b0, lp_ssp_din, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_ssp_frame (major_mode, ssp_frame, lr_ssp_frame, le_ssp_frame, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe1 (major_mode, pwr_oe1, lr_pwr_oe1, le_pwr_oe1, lp_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe2 (major_mode, pwr_oe2, lr_pwr_oe2, le_pwr_oe2, lp_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe3 (major_mode, pwr_oe3, lr_pwr_oe3, le_pwr_oe3, lp_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_oe4 (major_mode, pwr_oe4, lr_pwr_oe4, le_pwr_oe4, lp_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_lo (major_mode, pwr_lo, lr_pwr_lo, le_pwr_lo, lp_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_pwr_hi (major_mode, pwr_hi, lr_pwr_hi, le_pwr_hi, lp_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_adc_clk (major_mode, adc_clk, lr_adc_clk, le_adc_clk, lp_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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mux8 mux_dbg (major_mode, dbg, lr_dbg, le_dbg, lp_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
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// In all modes, let the ADC's outputs be enabled.
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assign adc_noe = 1'b0;
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@ -25,7 +25,7 @@ module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
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always @(posedge clk)
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begin
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case (state)
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0:
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0: // initialize
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begin
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if (cur_max_val >= ({1'b0, adc_d} + threshold))
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state <= 2;
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@ -36,7 +36,7 @@ module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
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else if (adc_d <= cur_min_val)
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cur_min_val <= adc_d;
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end
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1:
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1: // high phase
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begin
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if (cur_max_val <= adc_d)
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cur_max_val <= adc_d;
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@ -46,7 +46,7 @@ module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
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max_val <= cur_max_val;
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end
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end
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2:
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2: // low phase
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begin
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if (adc_d <= cur_min_val)
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cur_min_val <= adc_d;
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