mirror of
https://github.com/zerotier/ZeroTierOne.git
synced 2024-10-17 20:50:29 -07:00
e4e0be979e
The Hyperledger implementation (https://github.com/hyperledger/iroha-ed25519) contains changes to the assembly code to allow PIC. This in turn fixes compilation/linking of ZeroTier One when "full hardening" flags are used.
233 lines
5.5 KiB
ArmAsm
233 lines
5.5 KiB
ArmAsm
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# qhasm: int64 rp
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# qhasm: int64 xp
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# qhasm: int64 yp
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# qhasm: input rp
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# qhasm: input xp
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# qhasm: input yp
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# qhasm: int64 r0
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# qhasm: int64 r1
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# qhasm: int64 r2
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# qhasm: int64 r3
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# qhasm: int64 t0
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# qhasm: int64 t1
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# qhasm: int64 t2
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# qhasm: int64 t3
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# qhasm: int64 caller1
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# qhasm: int64 caller2
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# qhasm: int64 caller3
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# qhasm: int64 caller4
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# qhasm: int64 caller5
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# qhasm: int64 caller6
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# qhasm: int64 caller7
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# qhasm: caller caller1
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# qhasm: caller caller2
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# qhasm: caller caller3
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# qhasm: caller caller4
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# qhasm: caller caller5
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# qhasm: caller caller6
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# qhasm: caller caller7
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# qhasm: stack64 caller4_stack
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# qhasm: stack64 caller5_stack
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# qhasm: stack64 caller6_stack
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# qhasm: stack64 caller7_stack
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# qhasm: enter crypto_sign_ed25519_amd64_64_sc25519_add
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.text
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.p2align 5
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.globl _crypto_sign_ed25519_amd64_64_sc25519_add
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.globl crypto_sign_ed25519_amd64_64_sc25519_add
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_crypto_sign_ed25519_amd64_64_sc25519_add:
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crypto_sign_ed25519_amd64_64_sc25519_add:
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mov %rsp,%r11
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and $31,%r11
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add $32,%r11
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sub %r11,%rsp
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# qhasm: caller4_stack = caller4
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# asm 1: movq <caller4=int64#12,>caller4_stack=stack64#1
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# asm 2: movq <caller4=%r14,>caller4_stack=0(%rsp)
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movq %r14,0(%rsp)
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# qhasm: caller5_stack = caller5
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# asm 1: movq <caller5=int64#13,>caller5_stack=stack64#2
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# asm 2: movq <caller5=%r15,>caller5_stack=8(%rsp)
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movq %r15,8(%rsp)
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# qhasm: caller6_stack = caller6
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# asm 1: movq <caller6=int64#14,>caller6_stack=stack64#3
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# asm 2: movq <caller6=%rbx,>caller6_stack=16(%rsp)
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movq %rbx,16(%rsp)
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# qhasm: r0 = *(uint64 *)(xp + 0)
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# asm 1: movq 0(<xp=int64#2),>r0=int64#4
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# asm 2: movq 0(<xp=%rsi),>r0=%rcx
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movq 0(%rsi),%rcx
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# qhasm: r1 = *(uint64 *)(xp + 8)
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# asm 1: movq 8(<xp=int64#2),>r1=int64#5
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# asm 2: movq 8(<xp=%rsi),>r1=%r8
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movq 8(%rsi),%r8
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# qhasm: r2 = *(uint64 *)(xp + 16)
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# asm 1: movq 16(<xp=int64#2),>r2=int64#6
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# asm 2: movq 16(<xp=%rsi),>r2=%r9
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movq 16(%rsi),%r9
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# qhasm: r3 = *(uint64 *)(xp + 24)
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# asm 1: movq 24(<xp=int64#2),>r3=int64#2
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# asm 2: movq 24(<xp=%rsi),>r3=%rsi
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movq 24(%rsi),%rsi
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# qhasm: carry? r0 += *(uint64 *)(yp + 0)
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# asm 1: addq 0(<yp=int64#3),<r0=int64#4
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# asm 2: addq 0(<yp=%rdx),<r0=%rcx
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addq 0(%rdx),%rcx
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# qhasm: carry? r1 += *(uint64 *)(yp + 8) + carry
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# asm 1: adcq 8(<yp=int64#3),<r1=int64#5
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# asm 2: adcq 8(<yp=%rdx),<r1=%r8
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adcq 8(%rdx),%r8
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# qhasm: carry? r2 += *(uint64 *)(yp + 16) + carry
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# asm 1: adcq 16(<yp=int64#3),<r2=int64#6
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# asm 2: adcq 16(<yp=%rdx),<r2=%r9
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adcq 16(%rdx),%r9
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# qhasm: r3 += *(uint64 *)(yp + 24) + carry
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# asm 1: adcq 24(<yp=int64#3),<r3=int64#2
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# asm 2: adcq 24(<yp=%rdx),<r3=%rsi
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adcq 24(%rdx),%rsi
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# qhasm: t0 = r0
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# asm 1: mov <r0=int64#4,>t0=int64#3
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# asm 2: mov <r0=%rcx,>t0=%rdx
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mov %rcx,%rdx
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# qhasm: t1 = r1
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# asm 1: mov <r1=int64#5,>t1=int64#7
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# asm 2: mov <r1=%r8,>t1=%rax
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mov %r8,%rax
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# qhasm: t2 = r2
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# asm 1: mov <r2=int64#6,>t2=int64#8
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# asm 2: mov <r2=%r9,>t2=%r10
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mov %r9,%r10
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# qhasm: t3 = r3
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# asm 1: mov <r3=int64#2,>t3=int64#12
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# asm 2: mov <r3=%rsi,>t3=%r14
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mov %rsi,%r14
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# qhasm: carry? t0 -= *(uint64 *) &crypto_sign_ed25519_amd64_64_ORDER0
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# asm 1: sub crypto_sign_ed25519_amd64_64_ORDER0,<t0=int64#3
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# asm 2: sub crypto_sign_ed25519_amd64_64_ORDER0,<t0=%rdx
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sub crypto_sign_ed25519_amd64_64_ORDER0(%rip),%rdx
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# qhasm: carry? t1 -= *(uint64 *) &crypto_sign_ed25519_amd64_64_ORDER1 - carry
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# asm 1: sbb crypto_sign_ed25519_amd64_64_ORDER1,<t1=int64#7
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# asm 2: sbb crypto_sign_ed25519_amd64_64_ORDER1,<t1=%rax
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sbb crypto_sign_ed25519_amd64_64_ORDER1(%rip),%rax
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# qhasm: carry? t2 -= *(uint64 *) &crypto_sign_ed25519_amd64_64_ORDER2 - carry
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# asm 1: sbb crypto_sign_ed25519_amd64_64_ORDER2,<t2=int64#8
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# asm 2: sbb crypto_sign_ed25519_amd64_64_ORDER2,<t2=%r10
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sbb crypto_sign_ed25519_amd64_64_ORDER2(%rip),%r10
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# qhasm: unsigned<? t3 -= *(uint64 *) &crypto_sign_ed25519_amd64_64_ORDER3 - carry
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# asm 1: sbb crypto_sign_ed25519_amd64_64_ORDER3,<t3=int64#12
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# asm 2: sbb crypto_sign_ed25519_amd64_64_ORDER3,<t3=%r14
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sbb crypto_sign_ed25519_amd64_64_ORDER3(%rip),%r14
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# qhasm: r0 = t0 if !unsigned<
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# asm 1: cmovae <t0=int64#3,<r0=int64#4
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# asm 2: cmovae <t0=%rdx,<r0=%rcx
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cmovae %rdx,%rcx
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# qhasm: r1 = t1 if !unsigned<
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# asm 1: cmovae <t1=int64#7,<r1=int64#5
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# asm 2: cmovae <t1=%rax,<r1=%r8
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cmovae %rax,%r8
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# qhasm: r2 = t2 if !unsigned<
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# asm 1: cmovae <t2=int64#8,<r2=int64#6
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# asm 2: cmovae <t2=%r10,<r2=%r9
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cmovae %r10,%r9
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# qhasm: r3 = t3 if !unsigned<
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# asm 1: cmovae <t3=int64#12,<r3=int64#2
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# asm 2: cmovae <t3=%r14,<r3=%rsi
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cmovae %r14,%rsi
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# qhasm: *(uint64 *)(rp + 0) = r0
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# asm 1: movq <r0=int64#4,0(<rp=int64#1)
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# asm 2: movq <r0=%rcx,0(<rp=%rdi)
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movq %rcx,0(%rdi)
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# qhasm: *(uint64 *)(rp + 8) = r1
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# asm 1: movq <r1=int64#5,8(<rp=int64#1)
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# asm 2: movq <r1=%r8,8(<rp=%rdi)
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movq %r8,8(%rdi)
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# qhasm: *(uint64 *)(rp + 16) = r2
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# asm 1: movq <r2=int64#6,16(<rp=int64#1)
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# asm 2: movq <r2=%r9,16(<rp=%rdi)
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movq %r9,16(%rdi)
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# qhasm: *(uint64 *)(rp + 24) = r3
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# asm 1: movq <r3=int64#2,24(<rp=int64#1)
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# asm 2: movq <r3=%rsi,24(<rp=%rdi)
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movq %rsi,24(%rdi)
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# qhasm: caller4 = caller4_stack
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# asm 1: movq <caller4_stack=stack64#1,>caller4=int64#12
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# asm 2: movq <caller4_stack=0(%rsp),>caller4=%r14
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movq 0(%rsp),%r14
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# qhasm: caller5 = caller5_stack
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# asm 1: movq <caller5_stack=stack64#2,>caller5=int64#13
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# asm 2: movq <caller5_stack=8(%rsp),>caller5=%r15
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movq 8(%rsp),%r15
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# qhasm: caller6 = caller6_stack
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# asm 1: movq <caller6_stack=stack64#3,>caller6=int64#14
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# asm 2: movq <caller6_stack=16(%rsp),>caller6=%rbx
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movq 16(%rsp),%rbx
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# qhasm: leave
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add %r11,%rsp
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mov %rdi,%rax
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mov %rsi,%rdx
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ret
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