mirror of
https://github.com/RfidResearchGroup/proxmark3.git
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77 lines
3.1 KiB
C
77 lines
3.1 KiB
C
//-----------------------------------------------------------------------------
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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#include "clocks.h"
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#include "proxmark3_arm.h"
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void mck_from_pll_to_slck(void) {
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// switch main clk to slow clk, first CSS then PRES
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_SLOW_CLK;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) {};
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK | AT91C_PMC_CSS_SLOW_CLK;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) {};
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// disable the PLL
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AT91C_BASE_PMC->PMC_PLLR = 0x0;
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// disable main oscillator
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AT91C_BASE_PMC->PMC_MOR = 0;
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}
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void mck_from_slck_to_pll(void) {
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// worst case scenario, with MAINCK = 16MHz xtal, startup delay is 1.4ms
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// if SLCK slow clock runs at its worst case (max) frequency of 42kHz
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// max startup delay = (1.4ms*42k)/8 = 7.356 so round up to 8
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// UPDATE:
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// we observed on 10% of the devices very wrong initial slow clock RC TIA measures.
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// Bumping delay to 16 helps fixing the issue even on the most screwed RC.
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// enable main oscillator and set startup delay
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AT91C_BASE_PMC->PMC_MOR =
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AT91C_CKGR_MOSCEN |
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PMC_MAIN_OSC_STARTUP_DELAY(16);
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// wait for main oscillator to stabilize
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)) {};
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// PLL output clock frequency in range 80 - 160 MHz needs CKGR_PLL = 00
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// PLL output clock frequency in range 150 - 180 MHz needs CKGR_PLL = 10
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// PLL output is MAINCK * multiplier / divisor = 16MHz * 12 / 2 = 96MHz
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AT91C_BASE_PMC->PMC_PLLR =
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PMC_PLL_DIVISOR(2) |
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//PMC_PLL_COUNT_BEFORE_LOCK(0x10) |
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PMC_PLL_COUNT_BEFORE_LOCK(0x3F) |
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PMC_PLL_FREQUENCY_RANGE(0) |
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PMC_PLL_MULTIPLIER(12) |
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PMC_PLL_USB_DIVISOR(1);
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// wait for PLL to lock
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK)) {};
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// we want a master clock (MCK) to be PLL clock / 2 = 96MHz / 2 = 48MHz
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// datasheet recommends that this register is programmed in two operations
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// when changing to PLL, program the prescaler first then the source
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_SLOW_CLK;
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// wait for main clock ready signal
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) {};
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// set the source to PLL
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AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLL_CLK;
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// wait for main clock ready signal
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)) {};
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}
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