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cd028159be
* fix long option --jam * make room for one more bit for FPGA minor mode * new mode FPGA_HF_READER_MODE_SEND_JAM * implement jamming in Handle15693SampleFromReader
146 lines
4.5 KiB
Verilog
146 lines
4.5 KiB
Verilog
//-----------------------------------------------------------------------------
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// Pretend to be an ISO 14443 tag. We will do this by alternately short-
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// circuiting and open-circuiting the antenna coil, with the tri-state
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// pins.
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//
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// We communicate over the SSP, as a bitstream (i.e., might as well be
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// unframed, though we still generate the word sync signal). The output
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// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
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// -> ARM) is us using the A/D as a fancy comparator; this is with
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// (software-added) hysteresis, to undo the high-pass filter.
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//
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// At this point only Type A is implemented. This means that we are using a
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// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
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// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
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//
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// Jonathan Westhues, October 2006
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//-----------------------------------------------------------------------------
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module hi_simulate(
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ck_1356meg,
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pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
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adc_d, adc_clk,
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ssp_frame, ssp_din, ssp_dout, ssp_clk,
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dbg,
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mod_type
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);
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input ck_1356meg;
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output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
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input [7:0] adc_d;
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output adc_clk;
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input ssp_dout;
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output ssp_frame, ssp_din, ssp_clk;
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output dbg;
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input [3:0] mod_type;
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assign adc_clk = ck_1356meg;
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// The comparator with hysteresis on the output from the peak detector.
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reg after_hysteresis;
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reg [11:0] has_been_low_for;
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always @(negedge adc_clk)
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begin
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if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
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else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
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if (adc_d >= 224)
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begin
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has_been_low_for <= 12'd0;
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end
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else
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begin
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if (has_been_low_for == 12'd4095)
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begin
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has_been_low_for <= 12'd0;
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after_hysteresis <= 1'b1;
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end
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else
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begin
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has_been_low_for <= has_been_low_for + 1;
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end
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end
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end
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// Divide 13.56 MHz to produce various frequencies for SSP_CLK
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// and modulation.
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reg [8:0] ssp_clk_divider;
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always @(negedge adc_clk)
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ssp_clk_divider <= (ssp_clk_divider + 1);
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reg ssp_clk;
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always @(negedge adc_clk)
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begin
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if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
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// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
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ssp_clk <= ~ssp_clk_divider[7];
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else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
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// Get next bit at 212kHz
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ssp_clk <= ~ssp_clk_divider[5];
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else
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// Get next bit at 424Khz
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ssp_clk <= ~ssp_clk_divider[4];
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end
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// Produce the byte framing signal; the phase of this signal
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// is arbitrary, because it's just a bit stream in this module.
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reg ssp_frame;
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always @(negedge adc_clk)
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begin
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if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
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begin
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if (ssp_clk_divider[8:5] == 4'd1)
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ssp_frame <= 1'b1;
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if (ssp_clk_divider[8:5] == 4'd5)
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ssp_frame <= 1'b0;
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end
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else
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begin
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if (ssp_clk_divider[7:4] == 4'd1)
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ssp_frame <= 1'b1;
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if (ssp_clk_divider[7:4] == 4'd5)
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ssp_frame <= 1'b0;
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end
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end
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// Synchronize up the after-hysteresis signal, to produce DIN.
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reg ssp_din;
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always @(posedge ssp_clk)
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ssp_din = after_hysteresis;
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// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
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reg modulating_carrier;
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always @(*)
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if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
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modulating_carrier <= 1'b0; // no modulation
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else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
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modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
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else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
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modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
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else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
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modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
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else
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modulating_carrier <= 1'b0; // yet unused
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// Load modulation. Toggle only one of these, since we are already producing much deeper
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// modulation than a real tag would.
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assign pwr_hi = 1'b0; // HF antenna connected to GND
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assign pwr_oe3 = 1'b0; // 10k Load
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assign pwr_oe1 = 1'b0; // 33 Ohms Load
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assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
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// This is all LF and doesn't matter
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assign pwr_lo = 1'b0;
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assign pwr_oe2 = 1'b0;
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assign dbg = ssp_frame;
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endmodule
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