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5ea2a24839
* merge hf_rx_xcorr and hf_tx modes into one module with common ssp_clk and ssp_frame * get rid of most of the warnings when compiling the HF verilog sources * refactoring the constants in Verilog sources
156 lines
3.2 KiB
Verilog
156 lines
3.2 KiB
Verilog
//-----------------------------------------------------------------------------
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//
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// piwi, Feb 2019
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//-----------------------------------------------------------------------------
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module hi_get_trace(
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ck_1356megb,
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adc_d, trace_enable, major_mode,
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ssp_frame, ssp_din, ssp_clk
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);
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input ck_1356megb;
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input [7:0] adc_d;
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input trace_enable;
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input [2:0] major_mode;
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output ssp_frame, ssp_din, ssp_clk;
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// clock divider
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reg [6:0] clock_cnt;
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always @(negedge ck_1356megb)
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begin
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clock_cnt <= clock_cnt + 1;
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end
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// sample at 13,56MHz / 8. The highest signal frequency (subcarrier) is 848,5kHz, i.e. in this case we oversample by a factor of 2
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reg [2:0] sample_clock;
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always @(negedge ck_1356megb)
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begin
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if (sample_clock == 3'd7)
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sample_clock <= 3'd0;
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else
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sample_clock <= sample_clock + 1;
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end
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reg [11:0] addr;
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reg [11:0] start_addr;
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reg [2:0] previous_major_mode;
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reg write_enable1;
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reg write_enable2;
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always @(negedge ck_1356megb)
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begin
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previous_major_mode <= major_mode;
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if (major_mode == `FPGA_MAJOR_MODE_HF_GET_TRACE)
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begin
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write_enable1 <= 1'b0;
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write_enable2 <= 1'b0;
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if (previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched into GET_TRACE mode
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addr <= start_addr;
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if (clock_cnt == 7'd0)
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begin
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if (addr == 12'd3071)
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addr <= 12'd0;
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else
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addr <= addr + 1;
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end
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end
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else if (major_mode != `FPGA_MAJOR_MODE_OFF)
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begin
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if (trace_enable)
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begin
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if (addr[11] == 1'b0)
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begin
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write_enable1 <= 1'b1;
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write_enable2 <= 1'b0;
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end
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else
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begin
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write_enable1 <= 1'b0;
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write_enable2 <= 1'b1;
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end
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if (sample_clock == 3'b000)
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begin
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if (addr == 12'd3071)
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begin
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addr <= 12'd0;
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write_enable1 <= 1'b1;
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write_enable2 <= 1'b0;
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end
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else
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addr <= addr + 1;
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end
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end
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else
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begin
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write_enable1 <= 1'b0;
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write_enable2 <= 1'b0;
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start_addr <= addr;
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end
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end
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else // major_mode == `FPGA_MAJOR_MODE_OFF
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begin
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write_enable1 <= 1'b0;
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write_enable2 <= 1'b0;
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if (previous_major_mode != `FPGA_MAJOR_MODE_OFF && previous_major_mode != `FPGA_MAJOR_MODE_HF_GET_TRACE) // just switched off
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start_addr <= addr;
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end
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end
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// (2+1)k RAM
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reg [7:0] D_out1, D_out2;
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reg [7:0] ram1 [2047:0];
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reg [7:0] ram2 [1023:0];
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always @(negedge ck_1356megb)
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begin
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if (write_enable1)
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begin
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ram1[addr[10:0]] <= adc_d;
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D_out1 <= adc_d;
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end
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else
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D_out1 <= ram1[addr[10:0]];
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if (write_enable2)
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begin
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ram2[addr[9:0]] <= adc_d;
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D_out2 <= adc_d;
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end
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else
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D_out2 <= ram2[addr[9:0]];
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end
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// SSC communication to ARM
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reg ssp_clk;
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reg ssp_frame;
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reg [7:0] shift_out;
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always @(negedge ck_1356megb)
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begin
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if(clock_cnt[3:0] == 4'd0) // update shift register every 16 clock cycles
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begin
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if(clock_cnt[6:4] == 3'd0) // either load new value
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begin
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if (addr[11] == 1'b0)
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shift_out <= D_out1;
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else
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shift_out <= D_out2;
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end
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else // or shift left
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shift_out[7:1] <= shift_out[6:0];
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end
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ssp_clk <= ~clock_cnt[3]; // ssp_clk frequency = 13,56MHz / 16 = 847,5 kHz
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if(clock_cnt[6:4] == 3'b000) // set ssp_frame for 0...31
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ssp_frame <= 1'b1;
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else
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ssp_frame <= 1'b0;
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end
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assign ssp_din = shift_out[7];
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endmodule
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